24LC02 DATASHEET PDF

The IC 24LC01/24LC02 uses the I2C addressing proto- col and 2-wire serial interface which includes a bidirec- tional serial data bus synchronized by a clock. Microchip 24LC02 EEPROM are available at Mouser Electronics. Mouser offers inventory, pricing, & datasheets for Microchip 24LC02 EEPROM. Description, Bit/Bit Serial EePROM Write Protect Memory Chips. Company, Pronics. Datasheet, Download 24LC02 datasheet. Quote. Find where to.

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During data transfer, the data line must datasheet stable whenever the clock line is high. Serial clock data input. Since the device will not acknowledge during a write cycle, this can be used to determine when the cycle is complete this feature can be used to maximize bus throughput. After this period the first clock pulse is generated. Partial page write allowed.

If not, the chip will return to a standby state.

For relative timing, refer to timing diagrams. This happens during the ninth clock cycle. Commerical temperature range 0. Data Input Setup Time. Output Capacitance See Note. A page write is initiated the same as byte write, but the microcontroller does not send a stop condition after the first data word is clocked in.

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The microcontroller must terminate the page write sequence with a stop condition. Stresses exceeding the range specified under “Absolute Maxi.

Hardware controlled write protection. The device address word consist of daatsheet mandatory one, zero sequence for the first four most significant bits refer to the diagram show- ing the Device Address.

Data transfer may be initiated only when the. ACK polling can be initiated immediately. A write operation requires an 8-bit data word address following the device address word and acknowledgment. Clock and data transition. Time in which the bus must be free before a new transmission can start. Instead, after the EEPROM ac- knowledges the receipt of the first data word, the microcontroller can transmit up to seven more data words.

Data Input Hold Time. If the device is still busy with 244lc02. Once the stop condition for a write command has been issued from the master, the device initiates the internally timed write cycle.

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Characteristics Functional Description Timing Diagrams. The pin is open-drain driven and may be wired-OR with any number of other open-drain or open collector devices. Input Capacitance See Note. Internally organized with 8-bit words, the 1K requires a 7-bit data word address for random word addressing.

A read operation is initi- ated if this bit is high and a write operation is initiated if this bit is low. Internally organized with 8-bit words, the 2K requires an 8-bit data word address for random word addressing.

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24LC02 PDF Datasheet浏览和下载

Output Valid from Clock. Upon receipt of this ad- dress, the EEPROM will again respond with a zero and then clock in the first 8-bit data word. Functional operation of this device at other conditions beyond those listed in the specification is not implied and prolonged exposure to extreme conditions may affect device reliability. After receiving the 8-bit data word, the EEPROM will output a zero and the address- ing device, such as a microcontroller, must terminate the write sequence with a stop con- dition.

The device is optimized for use in many industrial and com. The SDA pin is bidirectional for serial data transfer. The higher data word address bits are not incremented, re- taining the memory page row location refer to Page write timing.

Search field Part name Part description. These three bits must compare to their corresponding hard-wired input pins. These are stress ratings only. Write operation with built-in timer.